VERIFICATION ENGINEER / SYSTEM VERILOG / UVM / PHYTHON

(Senior) Verification Engineer / System Verilog / UVM / Phython(m/f/d)Location: BarcelonaAre you passionate about microprocessor architecture? We need you! As a Senior Verification Engineer, you will work within the Verification Team and play a crucial role in ensuring the correctness and functionality of complex digital designs at the Register Transfer Level according to the specification, using advanced verification methodologies and tools to validate the designs.What we offer? Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona!Candies, coffee and free Spanish lessons included! (Visa sponsorship if required)Requirements:Master or PhDProficiency in SystemVerilog and UVMKnowledge of scripting languages (Python, Perl, Bash, TCL) and regression toolsExperience with simulation and simulation toolsKnowledge of revision control methodology and tools (git, svn)Experience in block level and sub-system or top level verificationExperience with formal and dynamic verificationStrong problem-solving skills and attention to detailExcellent communication and teamwork abilitiesFor further information you can reach me also on lh@eu-recruit.comBy applying to this role you understand that we may collect your personal data, store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)